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Network-on-chip architecture design based on mesh-of-tree deterministic routing topology.
Santanu Kundu
Santanu Chattopadhyay
Published in:
Int. J. High Perform. Syst. Archit. (2008)
Keyphrases
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interconnection networks
network on chip
routing algorithm
fault tolerant
multistage
parallel algorithm
message passing
routing protocol
ad hoc networks
wireless sensor networks
shortest path
multipath
image processing
energy consumption
routing problem
parallel computers