High Speed ASIC Architectures for Aggregate Signature over BLS12-381.
Kaoru MasadaRyohei NakayamaMakoto IkedaPublished in: IEICE Trans. Electron. (2023)
Keyphrases
- high speed
- low power
- hardware implementation
- integrated circuit
- high speed networks
- real time
- single chip
- digital signature
- design methodology
- neural network
- circuit design
- application specific
- signature scheme
- signature verification
- frame rate
- multiresolution
- hardware architecture
- information systems
- neural architectures
- high speed camera