Power and performance aware reconfigurable cache for CMPs.

Kamil Kedzierski Francisco J. Cazorla Roberto Gioiosa Alper Buyuktosunoglu Mateo Valero

Published in: IFMT (2010)

Keyphrases

multithreading
power consumption
low cost
prefetching
reconfigurable architecture
power distribution
power reduction
databases
data access
hardware implementation
shared memory
computational power
power management
hit rate
memory subsystem