Effect of Circuit Non-Idealities on Active On-Chip Delay Lines.

Published in: ISCAS (2019)

Keyphrases

power dissipation
high speed
analog vlsi
phase locked loop
circuit design
evolvable hardware
power consumption
low power
cmos technology
line segments
data sets
micron cmos
end to end
digital circuits
nm technology
chip design
digital signal processing
multipath
genetic algorithm