Evaluating the Memory Architecture of Next-Generation FPGA-SoCs for HPC.
Matthias GoebelKai Norman ClasenRobert DrehmelBen H. H. JuurlinkPublished in: HPCS (2019)
Keyphrases
- hardware architecture
- real time
- hardware implementation
- hardware design
- digital signal processors
- associative memory
- processing elements
- software implementation
- parallel architecture
- memory management
- high speed
- management system
- level parallelism
- dedicated hardware
- fpga implementation
- parallel hardware
- hardware architectures
- field programmable gate array
- signal processing
- pipelined architecture
- hardware software
- high performance computing
- fpga technology
- fpga device
- real time image processing
- reconfigurable hardware
- fault tolerance
- multithreading
- memory requirements
- memory access
- systolic array
- low cost
- parallel processing