A 4.5 mW/Gb/s 6.4 Gb/s 22+1-Lane Source Synchronous Receiver Core With Optional Cleanup PLL in 65 nm CMOS.
Robert ReutemannMichael RueggFran KeyserJohn BergkvistDaniel DrepsThomas ToiflMartin L. SchmatzPublished in: IEEE J. Solid State Circuits (2010)