A novel chip-multiprocessor architecture with optically interconnected shared L1 optical cache memory.
Pavlos ManiotisSavvas GitzenisLeandros TassiulasNikos PlerosPublished in: OFC (2014)
Keyphrases
- multiprocessor architecture
- memory subsystem
- memory access
- multithreading
- processor core
- production system
- speculative execution
- main memory
- memory bandwidth
- memory hierarchy
- random access memory
- dynamic random access memory
- data access
- cache misses
- ibm zenterprise
- distributed shared memory
- cache conscious
- shared memory multiprocessors
- memory management
- low cost
- garbage collection
- high speed
- level parallelism
- computational power
- instruction set
- processing units
- virtual memory
- computing power
- memory requirements
- operating system
- database management systems
- printed circuit boards
- database workloads
- data structure
- database systems
- embedded dram
- parallel computing
- access patterns
- artificial intelligence