A low power architecture for 1D median filter using carry look ahead adder.
Sharana BasappaP. Ravi BabuPublished in: Int. J. Adv. Intell. Paradigms (2021)
Keyphrases
- low power
- median filter
- vlsi architecture
- logic circuits
- power consumption
- low cost
- high speed
- power dissipation
- cmos technology
- median filtering
- image enhancement
- nm technology
- single chip
- mixed signal
- noise reduction
- data flow
- vlsi circuits
- impulse noise
- real time
- digital signal processing
- gate array
- image sensor
- signal processor
- motion detection
- structuring elements
- ultra low power
- power reduction
- vlsi implementation
- computational complexity
- pattern recognition