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A 9 Transistor SRAM Featuring Array-level XOR Parallelism with Secure Data Toggling Operation.
Zihan Yin
Annewsha Datta
Shwetha Vijayakumar
Ajey P. Jacob
Akhilesh Jaiswal
Published in:
ACM Great Lakes Symposium on VLSI (2024)
Keyphrases
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