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A 3.57 Gb/s/pin Low Jitter All-Digital DLL With Dual DCC Circuit for GDDR3 DRAM in 54-nm CMOS Technology.
Won-Joo Yun
Hyun-Woo Lee
Dongsuk Shin
Suki Kim
Published in:
IEEE Trans. Very Large Scale Integr. Syst. (2011)
Keyphrases
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cmos technology
mixed signal
low voltage
low power
high speed
spl times
power consumption
parallel processing
embedded dram
cmos image sensor
power dissipation
image sensor
low cost
hardware and software
silicon on insulator
dynamic range
packet loss