Altering LUT configuration for wear-out mitigation of FPGA-mapped designs.

Parthasarathy M. B. Rao Abdulazim Amouri Saman Kiamehr Mehdi Baradaran Tahoori

Published in: FPL (2013)

Keyphrases

risk management
hardware implementation
high speed
field programmable gate array
real time image processing
signal processing
hardware design
low cost
real time
optimal configuration
verilog hdl
lookup table
decision support system
color images
embedded systems
single chip
gray scale
digital images