Automating the sizing of transistors in CMOS gates for low-power and high-noise margin operation.
Azam BegPublished in: Int. J. Circuit Theory Appl. (2015)
Keyphrases
- low power
- high noise
- logic circuits
- power consumption
- cmos technology
- high speed
- low cost
- low contrast
- high power
- single chip
- vlsi circuits
- low power consumption
- image sensor
- power reduction
- noise free
- mixed signal
- digital signal processing
- power dissipation
- delay insensitive
- image processing
- real time
- low voltage
- impulse noise
- digital camera
- efficient implementation
- cmos image sensor
- nm technology
- ultra low power