A low-power ADPLL using feedback DCO quarterly disabled in time domain.
Chua-Chin WangChi-Chun HuangSheng-Lun TsengPublished in: Microelectron. J. (2008)
Keyphrases
- low power
- power consumption
- low cost
- user friendly
- high speed
- single chip
- high power
- wireless transmission
- phase locked loop
- vlsi circuits
- digital signal processing
- frequency domain
- vlsi architecture
- low power consumption
- logic circuits
- power saving
- signal processor
- long range
- power dissipation
- power reduction
- mixed signal
- image compression
- peer to peer
- gate array
- ultra low power
- image processing