Wire Topology Optimization for Low Power CMOS.
Paul ZuberOthman BahlousThomas IlnseherMichael RitterWalter StechelePublished in: IEEE Trans. Very Large Scale Integr. Syst. (2009)
Keyphrases
- low power
- power consumption
- high speed
- low cost
- single chip
- image sensor
- cmos technology
- vlsi circuits
- high power
- vlsi architecture
- digital signal processing
- low power consumption
- wireless transmission
- gate array
- mixed signal
- logic circuits
- power dissipation
- ultra low power
- power reduction
- delay insensitive
- nm technology
- long range