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ASIC design of power and area efficient programmable FIR filter using optimized Urdhva-Tiryagbhyam Multiplier for impedance cardiography.
Sudhanshu Janwadkar
Rasika Dhavse
Published in:
Microprocess. Microsystems (2024)
Keyphrases
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fir filters
single chip
design methodology
computationally efficient
circuit design
filter design
power consumption
image processing
high frequency
hardware architecture
vlsi implementation