A Flexible LDPC code decoder with a Network on Chip as underlying interconnect architecture
Carlo CondoGuido MaseraPublished in: CoRR (2011)
Keyphrases
- network on chip
- ldpc codes
- low density parity check
- power dissipation
- interconnection networks
- message passing
- multi processor
- decoding algorithm
- routing algorithm
- error correction
- network simulator
- packet switched
- power consumption
- turbo codes
- distributed video coding
- low power
- high speed
- low complexity
- real time
- distributed source coding
- channel coding
- cmos technology
- single processor
- data transfer
- data flow
- fault tolerant
- belief propagation
- digital signal processing
- bit rate
- wireless sensor networks