A 1.2 V, 33 ppm/°C, 40 nW, regeneration based BGR circuit for nanowatt CMOS LSIs.
Abhishek ShrivastavaAmandeep KaurMukul SarkarPublished in: ISOCC (2017)
Keyphrases
- circuit design
- analog vlsi
- high speed
- delay insensitive
- cmos technology
- low voltage
- vlsi circuits
- low power
- power consumption
- power dissipation
- digital circuits
- low cost
- power reduction
- analog circuits
- parallel processing
- logic circuits
- electronic circuits
- compression algorithm
- database
- power supply
- design considerations
- metal oxide semiconductor