120V/ns output slew rate enhancement technique and high voltage clamping circuit in high integrated gate driver for power GaN FETs.
Hsiang-An YangChao-Chang ChiuShin-Chi LaiJui-Lung ChenChih-Wei ChangChe-Hao MengKe-Horng ChenChin-Long WeyYing-Hsi LinChao-Cheng LeeJian-Ru LinTsung-Yen TsaiHsin-Yu LuoPublished in: ESSCIRC (2015)
Keyphrases
- high voltage
- multiple input
- phase locked loop
- image enhancement
- power consumption
- high speed
- operating conditions
- cmos technology
- network simulator
- normal operation
- power reduction
- duty cycle
- ad hoc networks
- partial discharge
- real time
- input data
- supervised learning
- case based reasoning
- wireless sensor networks
- image processing
- neural network