Fault Tolerant Technique for Processor Control Path to Mitigate SEUs in FPGA.
B. S. ChandrasekharS. DeepanjaliSk. Noor MahammadPublished in: iSES (2022)
Keyphrases
- fault tolerant
- fault tolerance
- fault isolation
- high speed
- distributed systems
- state machine
- digital signal
- single chip
- control system
- shortest path
- load balancing
- data acquisition
- low cost
- gate array
- multi agent
- systolic array
- computer architecture
- parallel processing
- safety critical
- interconnection networks
- evolvable hardware
- parallel architecture
- mobile agent system
- error detection
- field programmable gate array