A sub-2W 39.8-to-44.6Gb/s transmitter and receiver chipset with SFI-5.2 interface in 40nm CMOS.
Bharath RaghavanDelong CuiUllas SinghHassan MaarefiDave PiAnand VasaniZhi Chao HuangAfshin MomtazJun CaoPublished in: ISSCC (2013)
Keyphrases
- power supply
- high speed
- cmos technology
- user interface
- silicon on insulator
- received signal
- multiple input multiple output
- low cost
- low power
- power consumption
- metal oxide semiconductor
- human computer interaction
- analog vlsi
- nm technology
- user friendly
- focal plane
- parallel processing
- signal to noise ratio
- interface design
- circuit design
- operating system
- delay insensitive
- vlsi circuits
- channel state information
- x ray