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Test Instruction Set (TIS) for High Level Self-Testing of CPU Cores.
Saeed Shamshiri
Hadi Esmaeilzadeh
Zainalabedin Navabi
Published in:
Asian Test Symposium (2004)
Keyphrases
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level parallelism
instruction set
high level
floating point
application specific
computer architecture
memory access
multi core processors
embedded systems
data model
general purpose
low cost
memory subsystem