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Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors.

Rajeev R. RaoKaviraj ChopraDavid T. BlaauwDennis Sylvester
Published in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2007)
Keyphrases
  • error rate
  • test set
  • high speed
  • feature vectors
  • keypoints
  • equal error rate
  • lower error rates
  • computer vision
  • pattern recognition
  • circuit design
  • false discovery rate