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A 90nm CMOS 1.2v 6b 1GS/s two-step subranging ADC.

Pedro M. FigueiredoPaulo CardosoAna LopesCarlos FachadaNaoyuki HamanishiKen TanabeJoão C. Vital
Published in: ISSCC (2006)
Keyphrases
  • high speed
  • power consumption
  • post processing
  • cmos technology
  • low cost
  • real time
  • data sets
  • low power
  • image processing algorithms
  • circuit design
  • single chip
  • nm technology