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A 21-Gb/s Duobinary Transceiver for GDDR Interfaces With an Adaptive Equalizer.
Dongsuk Kang
Jae-Woo Park
Injae Park
Minsu Park
Xuefan Jin
Kyu-Dong Hwang
Dae-Han Kwon
Jung-Hoon Chun
Published in:
IEEE J. Solid State Circuits (2022)
Keyphrases
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computer simulation
multipath
user interface
high speed
database
website
adaptive learning
wireless systems
ultra wideband
visual interfaces
phase locked loop