Optimized On-Chip-Pipelined Mergesort on the Cell/B.E.

Rikard Hultén Christoph W. Kessler Jörg Keller

Published in: Euro-Par (2) (2010)

Keyphrases

high speed
low cost
analog vlsi
operating system
data flow
real time systems
architectural design
times faster
programmable logic
linear array
case study
high density
image sensor
single chip
memory access