A Novel Low-Power Clock Skew Compensation Circuit.

Rong Ji Liang Chen Gang Luo Xianjun Zeng Junfeng Zhang Yingjie Feng

Published in: ISVLSI (2008)

Keyphrases

low power
high speed
power consumption
logic circuits
power reduction
cmos technology

power dissipation
gate array
single chip
delay insensitive
duty cycle
wireless transmission

high power
low cost
vlsi circuits
power saving
real time
digital signal processing

image sensor
vlsi architecture
mixed signal
low power consumption
circuit design
nm technology