A Low-Power IF Circuit with 5 dB Minimum Input SNR for GFSK Low-IF Receivers.
Bo ZhaoGuangming YuTao ChenPengpeng ChenHuazhong YangHui WangPublished in: IEICE Trans. Electron. (2011)
Keyphrases
- low power
- high speed
- logic circuits
- low power consumption
- power consumption
- cmos technology
- low cost
- gate array
- power reduction
- power dissipation
- delay insensitive
- vlsi circuits
- single chip
- high power
- signal to noise ratio
- wireless transmission
- digital signal processing
- mixed signal
- vlsi architecture
- signal noise ratio
- power saving
- edge detection