Simulation Based Verification using Temporally Attributed Boolean Logic.

Subrat Kumar Panda Arnab Roy P. P. Chakrabarti Rajeev Kumar

Published in: VLSI Design (2007)

Keyphrases

boolean logic
truth values
model checking
temporal information
spatio temporal
asynchronous circuits
formal verification
verification method
database
image sequences
bayesian networks
natural language
signature verification