A 50-MHz CMOS quadrature charge sampling circuit with 66 dB SFDR.
Sami KarvonenTom A. D. RileyJuha KostamovaaraPublished in: ISCAS (1) (2004)
Keyphrases
- cmos technology
- high speed
- low power
- circuit design
- nm technology
- analog vlsi
- low voltage
- power dissipation
- power consumption
- delay insensitive
- random sampling
- parallel processing
- charge coupled devices
- charge coupled device
- sampling algorithm
- focal plane
- band limited
- low cost
- parameter space
- vlsi circuits
- sampling strategy
- sampling rate
- rotation invariant
- flip flops
- high frequency
- sample size
- real time
- electronic circuits
- fourier transform
- chip design