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Power profiling-guided floorplanner for 3D multi-processor systems-on-chip.
Ignacio Arnaldo
José Luis Risco-Martín
José Luis Ayala
José Ignacio Hidalgo
Published in:
IET Circuits Devices Syst. (2012)
Keyphrases
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multi processor
low cost
distributed systems
program execution
power consumption
ibm power processor
real time
image segmentation
bayesian networks
data management
shared memory
network on chip