Power optimization for clock network with clock gate cloning and flip-flop merging.

Shih-Chuan Lo Chih-Cheng Hsu Mark Po-Hung Lin

Published in: ISPD (2014)

Keyphrases

power consumption
duty cycle
power dissipation
cmos technology
high speed
low power
multiple input
peer to peer
network structure
wireless sensor networks
optimization problems
optimization algorithm
complex networks
input output
data flow
distribution network