Performance Analysis of Cache and Scratchpad Memory in an Embedded High Performance Processor.

Wanessa Pereira Dias Emilia Colonese

Published in: ITNG (2008)

Keyphrases

embedded processors
single chip
dynamic random access memory
memory subsystem
embedded dram
parallel implementation
memory hierarchy
low power
random access memory
memory requirements
memory access
low cost
instruction set
memory space
random access
processor core
computing power
main memory
cache misses
high speed