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A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process.

Ki Chul ChunYong-Gyu ChuJin-Seok HeoTae-Sung KimSoohwan KimHui-Kap YangMi-Jo KimChang-Kyo LeeJu-Hwan KimHyunchul YoonChang-Ho ShinSang-uhn ChaHyung-Jin KimYoung-Sik KimKyungryun KimYoung-Ju KimWon-Jun ChoiDae-Sik YimInkyu MoonYoung-Ju KimJunha LeeYoung ChoiYongmin KwonSung-Won ChoiJung-Wook KimYoon-Suk ParkWoongdae KangJinil ChungSeunghyun KimYesin RyuSeong-Jin ChoHoon ShinHangyun JungSanghyuk KwonKyuchang KangJongmyung LeeYujung SongYoungjae KimEun-Ah KimKyung-Soo HaKyoung-Ho KimSeok-Hun HyunSeung-Bum KoJung-Hwan ChoiYoung-Soo SohnKwang-Il ParkSeong-Jin Jang
Published in: ISSCC (2018)
Keyphrases
  • real time
  • high speed
  • closed form
  • low voltage
  • evolutionary algorithm
  • main memory
  • optimal solution