Performance improvements for SHA-3 finalists by exploiting microcontroller on-chip parallelism.
Pal-Stefan MurvayBogdan GrozaPublished in: CRiSIS (2011)
Keyphrases
- low cost
- single chip
- level parallelism
- multithreading
- control system
- parallel processing
- shared memory
- hash functions
- vlsi implementation
- design considerations
- massively parallel
- memory bandwidth
- analog vlsi
- real time
- high density
- high speed
- circuit design
- physical design
- cmos technology
- parallel implementation
- low power
- neural network