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Design of a 1.8 V 6-bit Folding Interpolation CMOS A/D Converter with a 0.93 [pJ/convstep] Figure-of-Merit.
Sanghoon Hwang
Junho Moon
Minkyu Song
Published in:
IEICE Trans. Electron. (2008)
Keyphrases
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analog to digital converter
figure of merit
circuit design
computer vision
power consumption
low power
mixed signal