Reducing power dissipation in CMOS circuits by signal probability based transistor reordering.
Razak HossainMenghui ZhengAlexander AlbickiPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (1996)
Keyphrases
- power dissipation
- power reduction
- power consumption
- low power
- cmos technology
- digital signal processing
- signal processing
- chip design
- vlsi circuits
- logic circuits
- nm technology
- low cost
- flip flops
- finite state machines
- analog circuits
- high speed
- neural network
- low voltage
- design methodology
- power saving
- image restoration
- image analysis
- computer vision