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SALAD: Achieving Symmetric Access Latency with Asymmetric DRAM Architecture.

Young Hoon SonHyunyoon ChoYuhwan RoJae W. LeeJung Ho Ahn
Published in: IEEE Comput. Archit. Lett. (2017)
Keyphrases
  • access latency
  • memory access
  • prefetching
  • main memory
  • cache hit ratio
  • data structure
  • management system
  • multi dimensional
  • data access
  • caching scheme
  • database
  • data collection
  • data broadcast