ARC: DVFS-Aware Asymmetric-Retention STT-RAM Caches for Energy-Efficient Multicore Processors.
Dhruv GajariaTosiron AdegbijaPublished in: CoRR (2024)
Keyphrases
- energy efficient
- multicore processors
- computing power
- wireless sensor networks
- operating system
- energy consumption
- sensor networks
- highly parallel
- parallel algorithm
- memory access
- parallel architectures
- data dissemination
- routing algorithm
- computing systems
- parallel programming
- base station
- high end
- power reduction
- energy efficiency
- data transmission
- main memory
- efficient implementation
- computational power