A 32-GS/s Front-End Sampling Circuit Achieving >39 dB SNDR for Time-Interleaved ADCs in 65-nm CMOS.
Lei ZhaoDengquan LiHenghui MaoRuixue DingZhangming ZhuPublished in: J. Circuits Syst. Comput. (2021)
Keyphrases
- cmos technology
- silicon on insulator
- circuit design
- metal oxide semiconductor
- low power
- nm technology
- high speed
- analog vlsi
- power consumption
- low voltage
- random sampling
- delay insensitive
- power dissipation
- low cost
- parallel processing
- back end
- vlsi circuits
- sampling algorithm
- monte carlo
- database
- image sensor
- mixed signal
- single chip
- integrated circuit
- sampling strategy
- chip design
- sample size