Timing verification of asynchronous sequential circuits with specifications - A method of reducing state transitions to be verified in detail.
Atsushi OhnishiYuji SugiyamaTakuji OkamotoPublished in: Systems and Computers in Japan (1996)
Keyphrases
- asynchronous circuits
- experimental evaluation
- high precision
- dynamic programming
- delay insensitive
- preprocessing
- cost function
- computational cost
- pairwise
- significant improvement
- state space
- segmentation method
- detection method
- clustering method
- high speed
- computational complexity
- objective function
- similarity measure
- databases
- error rate
- query evaluation
- state transition
- state transitions
- machine learning