A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling.
Ankur AgrawalSae Kyu LeeJoel SilbermanMatthew M. ZieglerMingu KangSwagath VenkataramaniNianzheng CaoBruce M. FleischerMichael GuillornMatt CohenSilvia M. MuellerJinwook OhMartin LutzJinwook JungSiyu KoswattaChing ZhouVidhi ZalaniJames BonannoRobert CasatutaChia-Yu ChenJungwook ChoiHoward HaynieAlyssa HerbertRadhika JainMonodeep KarKyu-Hyoun KimYulong LiZhibin RenScot RiderMarcel SchaalKerstin SchelmMichael ScheuermannXiao SunHung TranNaigang WangWei WangXin ZhangVinay ShahBrian W. CurranVijayalakshmi SrinivasanPong-Fei LuSunil ShuklaLeland ChangKailash GopalakrishnanPublished in: ISSCC (2021)
Keyphrases
- artificial intelligence
- physical design
- high speed
- structured prediction
- low cost
- knowledge representation
- training set
- response time
- expert systems
- probabilistic inference
- bayesian networks
- training process
- low power
- training examples
- test set
- ai systems
- chip design
- knowledge based systems
- intelligent systems
- supervised learning
- case based reasoning
- machine learning
- transmission electron microscopy
- cmos technology
- training phase
- graphical models
- learning algorithm