Login / Signup
PROTEUS : A Logic Verification System for Combinational Circuits.
Alberto L. Sangiovanni-Vincentelli
Ruey-Sing Wei
Published in:
ITC (1986)
Keyphrases
</>
asynchronous circuits
delay insensitive
logic circuits
model checking
logic synthesis
low power
digital circuits
data sets
artificial intelligence
expert systems
temporal logic
natural deduction