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A 3.0 Gb/s Throughput Hardware-Efficient Decoder for Cyclically-Coupled QC-LDPC Codes.

Qing LuJianfeng FanChiu-Wing ShamWai Man TamFrancis C. M. Lau
Published in: IEEE Trans. Circuits Syst. I Regul. Pap. (2016)
Keyphrases
  • ldpc codes
  • decoding algorithm
  • error correction
  • message passing
  • low complexity
  • rate allocation
  • low density parity check
  • turbo codes
  • image sequences
  • error detection
  • image transmission