A gate leakage reduction strategy for future CMOS circuits.

Mindaugas Drazdziulis Per Larsson-Edefors

Published in: ESSCIRC (2003)

Keyphrases

cmos technology
analog vlsi
delay insensitive
high speed
circuit design
vlsi circuits
low power
power consumption
low voltage
power dissipation
leakage current
long term
multiple input
real world
floating gate
single chip
parallel processing
low cost
power reduction
random access memory
neural network
data sets