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Instruction merging to increase parallelism in VLIW architectures.
Guillermo Payá Vayá
Javier Martín-Langerwerf
Florian Giesemann
Holger Blume
Peter Pirsch
Published in:
SoC (2009)
Keyphrases
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level parallelism
multi core processors
instruction set
parallel processing
learning process
parallel architectures
memory bandwidth
real time
learning algorithm
e learning
memory hierarchy