Florian Giesemann

Publication Activity (10 Years)

Years Active: 2009-2020
Publications (10 Years): 5

Top Topics

Multi Processor

Genetic Algorithm

Driver Assistance

Parallel Architectures

Top Venues

Publications

Florian Giesemann, Lukas Gerlach, Guillermo Payá Vayá
Evolutionary Algorithms for Instruction Scheduling, Operation Merging, and Register Allocation in VLIW Compilers. J. Signal Process. Syst. 92 (7) (2020)
Stephan Nolting, Guillermo Payá Vayá, Florian Giesemann, Holger Blume, Sebastian Niemann, Christian Müller-Schloer
Dynamic self-reconfiguration of a MIPS-based soft-core processor architecture. J. Parallel Distributed Comput. 133 (2019)
Stephan Nolting, Florian Giesemann, Julian Hartig, Achim Schmider, Guillermo Payá Vayá
Application-specific soft-core vector processor for advanced driver assistance systems. FPL (2017)
Florian Giesemann, Guillermo Payá Vayá, Lukas Gerlach, Holger Blume, Fabian Pflug, Gabriele von Voigt
Using a genetic algorithm approach to reduce register file pressure during instruction scheduling. SAMOS (2017)
Stephan Nolting, Guillermo Payá Vayá, Florian Giesemann, Holger Blume, Sebastian Niemann, Christian Müller-Schloer
Dynamic Self-Reconfiguration of a MIPS-Based Soft-Processor Architecture. IPDPS Workshops (2016)
Stephan Nolting, Guillermo Payá Vayá, Florian Giesemann, Holger Blume
Exploring Dynamic Reconfigurable CORDIC Co-Processors Tightly Coupled with a VLIW-SIMD Soft-Processor Architecture. ARC (2015)
Oliver Jakob Arndt, Daniel Becker, Florian Giesemann, Guillermo Payá Vayá, Christopher Bartels, Holger Blume
Performance evaluation of the Intel Xeon Phi manycore architecture using parallel video-based driver assistance algorithms. ICSAMOS (2014)
Florian Giesemann, Guillermo Payá Vayá, Holger Blume, Matthias Limmer, Werner Ritter
A comprehensive ASIC/FPGA prototyping environment for exploring embedded processing systems for advanced driver assistance applications. ICSAMOS (2014)
Guillermo Payá Vayá, Javier Martín-Langerwerf, Florian Giesemann, Holger Blume, Peter Pirsch
Instruction merging to increase parallelism in VLIW architectures. SoC (2009)