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Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked ICs.
Xin Zhao
Dean L. Lewis
Hsien-Hsin S. Lee
Sung Kyu Lim
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2011)
Keyphrases
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low power
power consumption
high speed
single chip
logic circuits
low power consumption
low cost
vlsi architecture
gate array
power dissipation
digital signal processing
ultra low power
cmos technology
vlsi circuits
power reduction
mixed signal
design considerations
real time