Improving Bounds for FPGA Logic Minimization.
Tim TodmanHaofan FuOskar MencerWayne LukPublished in: FPT (2007)
Keyphrases
- upper bound
- classical logic
- high speed
- objective function
- field programmable gate array
- automated reasoning
- lower and upper bounds
- worst case
- modal logic
- hardware implementation
- upper and lower bounds
- multi valued
- logical framework
- digital circuits
- asynchronous circuits
- real time image processing
- error bounds
- regularization term
- signal processing
- low cost
- real time
- computational properties
- single chip