Chip-Level Performance Maximization Using ASIS (Application-Specific Interconnect Structure) Wiring Design Concept for 45 nm CMOS Generation.
Noriaki OdaHironori ImuraNaoyoshi KawaharaMasayoshi TagamiHiroyuki KunishimaShuji SoneSadayuki OhnishiKenta YamadaYumi KakuharaMakoto SekineYoshihiro HayashiKazuyoshi UenoPublished in: IEICE Trans. Electron. (2007)
Keyphrases
- power dissipation
- application specific
- chip design
- cmos technology
- high speed
- nm technology
- circuit design
- low power consumption
- power consumption
- general purpose
- low power
- low cost
- single chip
- high bandwidth
- cmos image sensor
- cad cam
- databases
- integrated circuit
- dynamic reconfiguration
- building blocks
- relational databases
- metal oxide semiconductor
- design considerations
- high density
- software architecture
- digital signal processing
- physical design
- information management