Design of a Low Power, High Speed Complementary Input Folded Regulated Cascode OTA for a Parallel Pipeline ADC.
Manas Kumar HatiTarun Kanti BhattacharyyaPublished in: ISVLSI (2011)
Keyphrases
- low power
- high speed
- single chip
- low cost
- low power consumption
- vlsi architecture
- power consumption
- logic circuits
- digital signal processing
- cmos technology
- power dissipation
- gate array
- mixed signal
- power reduction
- high power
- ultra low power
- analog to digital converter
- parallel processing
- frame rate
- design process
- multiple output
- vlsi circuits
- digital camera
- hardware and software
- shared memory
- cmos image sensor
- nm technology
- design methodology
- image sensor